Phase Frequency Detector


  • The block diagram of phase frequency detector is shown in Figure 1
    Figure 1. Phase frequency  detector block diagram

    Figure 1. Phase frequency detector block diagram

  • Outputs digital pulses whose widths are proportional to the phase difference between RefClk and FbClk
  • Time domain waveforms, ref leading, ref lagging, with clock slips
  • Edge triggered, sensitive only to rising or falling edges of RefClk and FbClk
  • Ideally should be independent of duty-cycle of clocks
  • State diagram of PFD which is sensitive to rising edge of RefClk clock

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    Figure 1. State diagram of phase frequency detector
  • 3-state phase detector
  • limited lock range : f_{out}-f_o < 2\pi K_{vco} K_{pd}
  • Cycle slips
  • Reset Delay ensures minimum width on output pules to avoid dead zones
  • Symmetric NAND used to balance equalize delays from both inputs?
  • PFD fails as Treset approaches Tref -> limit cycles
    – Challenge for Gb/sec IO links
    – Pulsed-flop designs can be faster

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