Phase Locked Loop

A Phase Locked Loop abbreviated as PLL, is a negative feedback system where an oscillator-generated signal is phase and frequency locked to a reference signal. PLLs are used to synthesize frequencies ranging from fraction of Hz to hundreds of GHz. PLLs are widely used in electronic circuits, wired and wireless communication systems, etc.,


Figure 1 illustrates the block diagram of a phase locked loop. It comprises the following building blocks:

  • Phase-Frequency Detector (PFD) : Outputs a digital pulse whose width is proportional to phase difference between reference input and feedback clocks
  • Charge Pump (CP) : Converts input digital pulse to analog error current
  • Loop Filter (LF) : Integrates error current to generate VCO control voltage
  • Voltage Controlled Oscillator : Ouputs a low voltage swing oscillating signal with frequency
    proportional to control voltage
  • Level Shifter (LS) : Amplifies VCO levels to full-swing
  • Feedback Divider : Divides incoming VCO clock to generate FBCLK clock
Figure 1. Block diagram of a phase locked loop

Figure 1. Block diagram of a phase locked loop

Based on the implementation or construction of elements of PLL, they are broadly classified into three types

  • Analog PLL (APLL) : If all the elements of PLL are analog and linear, then the PLLs are called analog or linear PLLs
  • Digital PLL (DPLL) : If the phase detector and charge pump are constructed using digital blocks (3-state PD using EXOR gates and chargepump), they are called digital PLLs
  • All Digital PLL (ADPLL) : If all the elements of PLL are made of digital elements then they are called all digital PLLs


  • Frequency Synthesis (e.g. generating a 1 GHz clock from a 100 MHz reference)
  • Extracting a clock from a random data stream (e.g. serial-link receiver)

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